One of the major bottlenecks in today's high speed computers is the difficulty of fetching data rapidly from a large memory. One of the difficulties is that it requires at least one addition to form each new address. The incrementing of a program counter can be viewed as the addition of one. Many times, more than one addition is required, and as we discussed above polynomial additions require time. That is one of the reasons that address forming mechanisms in large computers are almost always pipelined. As long as the pipeline remains full, one item per clock cycle can be fetched from memory, but if two successive items must be fetched from the same memory bank, then the computer misses a step and must do nothing for one clock pulse. Since residue addition is faster than binary addition, the address pipeline on a residue computer with residue addressing can be shortened, and therefore the computer can access memory easier.
In general pipelines are desirable, but what is more desirable is to shorten or eliminate them. They are extremely inefficient for situations in which data and algorithms do not have a regular structure. That is why modern supercomputers have both scalar and pipelined arithmetic units. The proposed architecture would eliminate the pipelines for the operations of rational add, subtract, multiply, and divide. Arithmetic pipelines would only be necessary for integer divide, rational scaling to handle overflow, and translation from residue to polynomial. It would not be necessary to have separate scalar and vector processing units for add, subtract, multiply and divide.